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description the HSDL-3210 is one of a new generation of low-cost infrared (ir) transceiver modules from avago technologies. it features one of the smallest footprint in the industry at 2.5 h x 8.0 w x 3.0 d mm. although the supply voltage can range from 2.7 v to 3.6 v, the led is driven by an internal constant current source of 60 ma at sir data rates and 150 ma at mir data rates. the HSDL-3210 incorporates the capability for adjustable optical power. the optical power can be adjusted lower when the nominal desired link distance is very short. at 5 cm link distance, only 6% of the full power is required. the HSDL-3210 supports the serial interface for transceiver control specification that provides a common interface between the transceiver and controller. it is also designed to interface to input/ output logic circuits as low as 1.5 v. features fully compliant to irda 1.4 low power specification from 9.6 kbit/s to 1.15 mbit/s ultra small surface mount package minimal height: 2.5 mm ? cc from 2.7 to 3.6 volts interface to 1.5 volts input/output logic circuits withstands 100 mv p-p power supply ripple typically adjustable optical power for link distance from 5 to 20 cm low shutdown current ?10 na typical complete shutdown ?txd, rxd, pin diode three optional external components temperature performance guaranteed, -25 c to 85 c integrated emi shield iec60825-1 class 1 eye safe edge detection input ?prevents the led from long turn on time applications mobile telecom ?cellular phones ?pagers ?smart phones data communication ?pdas ?portable printers digital imaging ?digital cameras ?photo-imaging printers HSDL-3210 irda?compliant low power 1.15 mbit/s infrared transceiver data sheet
2 application support information the application engineering group in avago technologies is available to assist you with the technical understanding associated with HSDL-3210 infrared transceiver module. you can contact them through your local avago sales representatives for additional details. ordering information part number packaging type package quantity HSDL-3210-021 tape and reel front view 2500 application circuit i/o pin configuration table pin symbol description notes 1 gnd ground connect to system ground. 2 iov cc input/output v cc connect to asic logic controller v cc voltage. 3v cc supply voltage regulated, 2.7 to 3.6 volts 4 sclk serial clock use as clock input pin for programming mode. see table 1 for details. 5 sd shut down active high this pin must be driven either high or low, do not float the pin. 6 rxd/srdat receiver data output. output is a low pulse when a light pulse is received. srdat is the read active low data for the serial transceiver control (stc). do not float this pin. 7 txd/swdat transmitter data input/ logic high turns on the led. if held high longer than ~20 s, the led serial write data is turned off. swdat is the write data for the serial transceiver control (stc). do not float this pin. 8 vled led supply voltage may be unregulated, 2.7 to 5.5 volts. - shield emi shield connect to system ground via a low inductance trace. for best performance, do not connect to gnd directly at the part. 87654321 rear view figure 1. functional block diagram of HSDL-3210. figure 2. rear view diagram with pin-out. 7 adjustable optical power 6 5 8 4 3 2 1 c3 0.47 ? c1 6.8 ? txd/swdat vled sclk gnd sd rxd/srdat i/o v cc v cc shield c2 1.0 ? serial transceiver control
3 serial interface for transceiver control the serial interface for transceiver control (stc) is used to control and program the features of the transceiver. these features include input/output (i/o) control, optical power adjustment and shut down. table 1. serial interface for transceiver control ?write data format address [2-0] index [3-0] c data irda data ?ata rates sir (2.4 to 115.2 kbps) 000 0001 1 00000000 mir (0.576, 1.152 mbps) 000 0001 1 00000001 i/o control sd normal mode 000 0000 1 xxxxxxx1 sd sleep mode 000 0000 1 xxxxxxx0 rxd disable 000 0000 1 xxxxxx0x rxd enable 000 0000 1 xxxxxx1x txd disable 000 0000 1 xxxxx0xx txd enable 000 0000 1 xxxxx1xx optical power adjustment 10% link distance 000 0010 1 00xxxxxx 25% link distance 000 0010 1 01xxxxxx 50% link distance 000 0010 1 10xxxxxx 100% link distance 000 0010 1 11xxxxxx the stc requires three signals: a serial clock (sclk) that is used for timing, and two unidirectional lines multiplexed with the transmitter (write) txd/swdat and receiver (read) rxd/srdat infrared signal lines. the HSDL-3210 supports the write function to disable/enable the txd line, disable/enable the rxd line and 4-level optical power adjustment. a set of commands is provided to handle the programming control features. the general command format is shown in figure 3. the HSDL-3210 stc write data commands are shown in table 1. figure 3. general command format. address [2-0] index [3-0] c data recommended application circuit components component recommended value notes c1 6.8 f, 20%, tantalum 1 c2 1.0 f, 20%, tantalum c3 0.47 f, 20%, ceramic note: 1. c1, which is optional, must be placed within 0.7 cm of the HSDL-3210 to obtain optimum noise immunity.
4 table 2. serial interface for transceiver control ?read data format address [2-0] index [3-0] c data irda data ?ata rates sir (2.4 to 115.2 kbps) 000 0001 0 00000000 mir (0.576, 1.152 mbps) 000 0001 0 00000001 i/o control sd normal mode 000 0000 0 xxxxxxx0 sd sleep mode 000 0000 0 xxxxxxx1 rxd disable 000 0000 0 xxxxxx0x rxd enable 000 0000 0 xxxxxx1x txd disable 000 0000 0 xxxxx0xx txd enable 000 0000 0 xxxxx1xx optical power adjustment 10% link distance 000 0010 0 00xxxxxx 25% link distance 000 0010 0 01xxxxxx 50% link distance 000 0010 0 10xxxxxx 100% link distance 000 0010 0 11xxxxxx id manufacturer 000 1111 0 00000001 product 000 1111 0 01000001 . transceiver i/o truth table stc sd mode sclk sd txd led receiver rxd notes normal mode low low high on don? care not valid 2,3 low off irda signal low 4,5 no signal high sleep mode don? care off don? care high 6 don? care don? care high don? care off don? care high 6 notes: 2. if txd is stuck in the high state, the led will turn off after about 14 s. 3. rxd will echo the txd signal while txd is transmitting data. 4. in-band irda signals and data rates 1.152 mbps. 5. rxd logic low is pulsed response. 6. rxd logic high during shutdown is a weak pull up (equivalent to an approximately 300 k ? resistor).
5 absolute maximum ratings for implementations where case to ambient thermal resistance is 50 c/w. parameter symbol min. max. units storage temperature t s -40 100 c operating temperature t a -25 85 c led supply voltage v led 0 6.5 v supply voltage v cc 0 6.5 v input/output voltage iov cc 0v cc v input voltage: txd, sclk, sd v i 0v cc + 0.5 v output voltage: rxd v o -0.5 v cc + 0.5 v caution: the bicmos inherent to this design of this component increases the component? susceptibility to damage from electrostatic discharge (esd). it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. recommended operating conditions parameter symbol min. max. units conditions notes operating temperature t a -25 85 c supply voltage v cc 2.7 3.6 v logic input voltage logic high v ih 2/3 iov cc iov cc v 1.5 v iov cc 3.6 v for txd ,sclk, sd logic low v il 0 1/3 iov cc v 1.5 v iov cc 3.6 v logic high receiver ei h 0.0081 500 mw/cm 2 for in-band signals 7 input irradiance eih 115.2kb/s (sir) 0.0225 500 mw/cm 2 0.576 mb/s in-band 7 signals 1.15 mb/s (mir) logic low receiver input ei l 0.3 w/cm 2 for in-band signals. input/output voltage iov cc 1.5 v cc v receiver data rate 0.0024 1.152 mb/s
6 electrical and optical specifications specifications hold over the recommended operating conditions unless otherwise noted. unspecified test conditions may be anywhere in their operating range. all typical values are at 25 c and 3.0 v unless otherwise noted. parameter symbol min. typ. max. units conditions notes receiver rxd output voltage logic high v oh iov cc -0.2 iov cc vi oh =-200 a, ei 0.3 w/cm 2 logic low v ol 0 0.4 v i ol =200 a8 viewing angle 2 1/2 30 peak sensitivity wavelength p 880 nm rxd pulse width (sir) t pw (sir) 1 7.5 sc l =10 pf 8,9 rxd pulse width (mir) t pw (mir) 200 750 ns c l =10 pf 9 rxd rise and fall times t r , t f 25 100 ns c l =10 pf receiver latency time t l 25 50 s10 receiver wake up time t rw 30 100 s11 transmitter radiant intensity (sir) ie h 4 15 28.8 mw/sr t a =25 c, 1/2 15 , txd v ih radiant intensity (mir) ie h 9 30 72 mw/sr t a =25 c, 1/2 15 , txd v ih peak wavelength p 875 nm spectral line half width ? 1/2 35 nm viewing angle 2 1/2 30 60 optical pulse width (sir) tpw 1.41 1.6 2.23 s tpw(txd) = 1.6 s optical pulse width (mir, iov cc 1.5 v) tpw 148 217 260 ns tpw(txd) = 217 ns optical rise and fall times (sir) tr (ei) 50 600 ns tpw(txd) = 1.6 s tf (ei) optical rise and fall times (mir) tr (ei) 30 40 ns tpw(txd) = 1.6 s tf (ei) led current on (sir) i vled 60 72 ma v vled =v cc =3.6 v, v i (txd) v ih on (mir) i vled 150 180 ma v vled =v cc =3.6 v, v i (txd) v ih current off i vled 0.005 1 sv vled =v cc =3.6 v, v i (txd) v il transceiver txd input current high i h 10 200 na v i v ih low i l -10 -200 na 0 v i v il supply current shutdown i cc1 0.01 av cc =3.6 v, v sd v cc - 0.5, t a =25 c idle i cc2 300 450 av cc =3.6 v, v i (txd) v il ,ei=0 active, i cc3 0.8 3.0 ma v cc =3.6 v, v i (txd) v il 12,13 receive notes: 7. an in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 nm p 900 nm, and the pulse characteristics are compliant with the irda serial infrared physical layer link specification. 8. for in band signals 1.152 mbps where 9 w/cm 2 ei 500 mw/cm 2 . 9. for 0.576 mbps in band signals 1.152 mbps where 22.5 w/cm 2 ei 500 mw/cm 2 . 10. latency is defined as the time from the last txd light output pulse until the receiver has recovered full sensitivity. 11. receiver wake up time is measured from the sd pin high to low transition or v cc power on, to valid rxd output. 12. typical values are at ei = 10 mw/cm 2 . 13. maximum value is at ei = 500 mw/cm 2 .
7 figure 4. rxd output waveform. figure 5. led optical waveform. figure 6. txd ?tuck on?protection waveform. figure 7. receiver wakeup time waveform. t f v oh 90% 50% 10% v ol t pw t r t f led off 90% 50% 10% led on t pw t r t pw (max.) txd led rx light t rw rxd sd
8 package dimensions figure 8. package outline dimensions. 2.85 mounting center 4.0 1.025 unit: mm tolerance: ?0.2 mm coplanarity: 0.1 mm max. c l 2.5 4.0 8.0 2.05 2.55 emitter receiver 0.35 0.65 0.80 c l 3.325 6.65 0.6 2.9 3.0 1.85 2.2 coplanarity: 0 to -0.2 mm 1.25 1.05 1.175 pin 1
9 tape and reel dimensions figure 9. tape and reel dimensions. 16.4 + 2 0 21 ?0.8 unit: mm b c ? 13.0 ?0.5 2.0 ?0.5 2.0 ?0.5 label 3.4 ?0.1 8.4 ?0.1 8.0 ?0.1 4.0 ?0.1 1.5 ?0.1 7.5 ?0.1 16.0 ?0.2 1.75 ?0.1 ? 1.5 + 0.1 0 0.4 ?0.05 2.8 ?0.1 polarity pin 8: led a pin 1: cx option # "b" "c" quantity 001 021 178 330 60 80 500 2500 empty parts mounted leader empty (40 mm min.) (400 mm min.) (40 mm min.) progressive direction r 1.0 detail a detail a unit: mm
10 recommended storage conditions storage temp. 10?c to 30?c relative humidity below 60% rh time from unsealing to soldering after removal from the bag, the parts should be soldered within three days if stored at the recom- mended storage conditions. figure 10. baking conditions chart. baking conditions if the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. packaging temp. time in reels 60?c 48 hours in bulk 100?c 4 hours 125?c 2 hours 150?c 1 hour baking should only be done once. moisture-proof packaging all HSDL-3210 options are shipped in moisture-proof packaging. once opened, moisture absorption begins. this product is compliant to jedec level 4. units in a sealed moisture-proof package package is opened (unsealed) environment less than 30?, and less than 60% rh package is opened less than 72 hours perform recommended baking conditions no baking is necessary yes no no yes
11 reflow profile process zone symbol ? t maximum ? t/ ? time heat up p1, r1 25?c to 125?c 4?c/s solder paste dry p2, r2 125?c to 170?c 0.5?c/s solder reflow p3, r3 170?c to 230?c (245?c at 10 seconds max.) 4?c/s p3, r4 230?c to 170?c ??c/s cool down p4, r5 170?c to 25?c ??c/s figure 11. reflow graph. the reflow profile is a straight line representation of a nominal temperature profile for a convec- tive reflow solder process. the temperature profile is divided into four process zones, each with different ? t/ ? time tempera- ture change rates. the ? t/ ? time rates are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and HSDL-3210 castellation i/o pins are heated to a temperature of 125 c to activate the flux in the solder paste. the temperature ramp up rate, r1, is limited to 4 c per second to allow for even heating of both the pc board and HSDL-3210 castellation i/o pins. process zone p2 should be of sufficient time duration (> 60 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder, usually 170 c (338 f). process zone p3 is the solder reflow zone. in zone p3, the tem- perature is quickly raised above the liquidus point of solder to 230 c (446 f) for optimum results. the dwell time above the liquidus point of solder should be between 15 and 90 seconds. it usually takes about 15 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. beyond a dwell time of 90 seconds, the inter- metallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 170 c (338 f), to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed ? c per sec- ond maximum. this limitation is necessary to allow the pc board and HSDL-3210 castellation i/o pins to change dimensions evenly, putting minimal stresses on the HSDL-3210 transceiver. 0 t-time (seconds) t temperature ( c) 200 170 125 100 50 50 150 100 200 250 300 150 183 230 p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 25 r1 r2 r3 r4 r5 90 sec. max. above 183 c max. 245 c
12 figure 12. stencil and pcba. 1.1 recommended land pattern appendix a : smt assembly application note 1.0 solder pad, mask and metal solder stencil aperture figure 13. land pattern. metal stencil for solder paste printing land pattern pcba stencil aperture solder mask 0.60 1.25 1.75 1.35 0.10 0.475 1.425 2.375 3.325 c l mounting center shield solder pad fiducial 2.05 0.775 unit: mm
13 figure 15. adjacent land keep-out and solder mask areas. stencil thickness, t (mm) aperture size (mm) length, l width, w 0.152 mm 2.60 0.05 0.55 0.05 0.127 mm 3.00 0.05 0.55 0.05 figure 14. solder stencil aperture. 1.2 recommended metal solder stencil aperture it is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. this is to ensure ad- equate printed solder paste vol- ume and no shorting. see the table below the drawing for com- binations of metal stencil aper- ture and metal stencil thickness that should be used. aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern. 1.3 adjacent land keepout and solder mask areas adjacent land keep-out is the maximum space occupied by the unit relative to the land pat- tern. there should be no other smd components within this area. the minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm . it is recommended that two fiducial crosses be placed at mid-length of the pads for unit alignment. note: wet/liquid photo- imageable solder resist/mask is recommended. apertures as per land dimensions l w t 0.2 3.0 8.2 solder mask 3.1 units: mm
14 appendix b: pcb layout suggestion the following pcb layout shows a recommended layout that should result in good electrical and emi performance. things to note: 1. the ground plane should be continuous under the part, but should not extend under the shield trace. 2. the shield trace is a wide, low inductance trace back to the system ground. 3. c1 is an optional v cc filter capacitor. it may be left out if the v cc is clean. 4. v led can be connected to either unfiltered or unregulated power. if c1 is used, and if v led is connected to v cc , the connection should be before the c1 cap. figure 16. pcb layout suggestions. top layer bottom layer a reference layout of a 2-layer avago evaluation board for HSDL-3210 based on the guidelines stated above is shown below. for more details, please refer to avago application note 1114, infrared transceiver pc board layout for noise immunity.
15 appendix c: general application guide for the HSDL-3210 infrared irda compliant 1.15 mb/s transceiver description the HSDL-3210, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as pdas, as well as small embedded mobile products such as digital cameras and cellular phones. it is fully compliant to irda 1.3 low power specification from 9.6 kb/s to 1.152 mb/s, and supports hp-sir and tv remote modes. the design of the HSDL-3210 also includes the following unique features: ?supports the serial interface for transceiver control (stc) specification. ?low passive component count. ?shutdown mode for low power consumption requirement. ?interface to input/output logic circuits as low as 1.5 v. ?adjustable optical power management interface to recommended i/o chips the HSDL-3210? txd data input is buffered to allow for cmos drive levels. no peaking circuit or capacitor is required. data rate from 9.6 kb/s up to 1.152 mbp/s is available at the rxd pin. the block diagram below shows how the ir port fits into a mobile phone and pda platform. pcmcia controller cpu for embedded application ir ram rom touch panel rs232c driver com port pda platform lcd panel transceiver mod/ de-modulator speaker rf interface audio interface user interface microcontroller dsp core asic controller ir microphone mobile phone platform figure 17. mobile phone and pda platform diagrams.
16 serial interface transceiver control (stc) HSDL-3210 supports the serial interface for transceiver control specification that provides a common interface between the transceiver and controller. stc comprises a 3-wire interface: txd/swdat, rxd/ardat and sclk. this 3-wire interface abolishes the use of different modes and logic pins of existing transceivers. instead registers on board the transceiver store operating modes and states, thus electrical interface can be standardized across different vendors and transceivers. the diagram below shows the stc i/o between the transceiver and the irda controller. in normal operation, the txd and rxd carry ir transmit and receive signals. in stc mode, swdat and srdat carry command and responses to and from the transceiver respectively. activity on the sclk line determines whether the trans- ceiver is to operate in the normal or stc mode. please refer to avago application note 1270 serial transceiver control for infrared transceivers for further information on implementing stc using hsdl- 3210 as well as the lists of registers supported by hsdl- 3210. stc normal mode infrared controller (master) transceiver (slave) txd rxd sclk stc command / response mode infrared controller (master) transceiver (slave) swdat (write command) srdat (send responses) sclk (clock command / response) figure 18. stc block diagram.
17 figure 19. general command format. stc bus protocol and timing diagrams bus protocol a set of commands is provided to handle the various transactions between the master and the slave. the general format is shown in figure 19 whereby communica- tions consist of a mandatory command phase followed by an optional response phase. the response phase occurs only when the slave needs to respond to a command. the command format consists of either 2 or 3 bytes command. the first byte, which is manda- tory and common to all trans- actions, consists of the address/ index/control bits. there are two control fields. the first one is the ??field which determines whether the command is a read or write operation or to act as a qualifier for a special operation. the second one is the ?ndx field whereby certain patterns define special transactions while others are for normal data trans- actions. the ?ddr?field is used to specify which transceiver the command is for. in a single transceiver system, this field is set to ?00? the second byte contains the data payload for a 2 byte com- mand. for a 3 byte command, this second byte is an 8 bit extended index. the third byte is the data payload when the extended index is used. addr (3) indx (4) c (1) 0 7 1st byte data (slave response) or e_indx (8) 0 7 2nd byte data (slave response) (8) 0 7 3rd byte figure 20. write command phase format. addr [2:0] indx [3:0] data addr [2:0] e_indx[7:0] 1 1111 1 data read transactions read transactions occur when the master queries the internal regis- ters of the slave. the initial com- mand phase is always followed by the response phase from the slave as shown below. addr [2:0] indx [3:0] 0 addr [2:0] e_indx[7:0] 1111 0 data figure 21a. read command phase format. figure 21b. slave response format. write transactions write transactions are when the master writes data to the slave to select the slave? operational mode. this requires only the command phase as shown below.
18 bus timing diagrams the bus timings are designed to be simple and to minimize the effects of timing skew. this sec- tion discusses some key points with regard to bus timings and illustrates typical stc transac- tions with the use of waveforms. bus timing notes 1. data is transferred in little endian order, that is, the lsb on the first byte is transmitted first and the msb of the second or third byte is transmitted last. 2. there are no gaps between bytes in the command or response phases. 3. each byte in the command and response phase is preceded by a start bit on the sclk line. 4. for data sampling and clocking, 4.1. input data is sampled on the rising edge of sclk. 4.2. output data from the con- troller is clocked out on the falling edge of sclk. 4.3. output data from the slave is clocked out on the rising edge of sclk. 5. the first low-to-high transition of sclk indicates that an stc transition is pending. on re- ceipt of his rising edge, the slave will disable the led. the next sclk low-to-high transition indicates the start cycle, fol- lowed by the command phase (which the controller puts out on the swdat line). the led needs to be disabled since txd and swdat are multiplexed. if the led is not disabled, then the led will pulse according to the swdat bit stream. 6. the led is re-enabled (by the slave) on the last sclk of the stc transaction bit stream. normal infrared transmission can resume. no sclk transi- tions should take place until the next stc transaction else the led will be disabled. 7. the response from the slave is carried on the srdat line, which is multiplexed with rxd. the detector is (internally) dis- abled by the slave during the response phase. this is to pre- vent stray ir transitions from corrupting the srdat bit stream. 8. during a read transaction, the controller holds the swdat line low for 1 clock after sending the address and index byte. it then holds it high and low for 3 clocks before the end of the transaction. this is to allow the transceiver to monitor the im- pending end of a transaction rather than by counting pulses. 9. when powered up, the trans- ceiver is not ready to perform ir transmissions. the controller has to initialize the transceiver. the brief powered up sequences are: 9.1. on power up, an inter- nally generated signal in the transceiver sets the 3 con- trol registers: a) control register 0: ?bit 0: shutdown mode ?bit 1: rxd disabled ?bit 2: led disabled b) control register 1: ?bit 0-7: sir mode c) control register 2: ?bit 0-7: power at 100% level 9.2. the controller has to initial- ize the transceiver by: a) hold swdat low b) toggle sclk for at least 30 cycles the transceiver is in stc mode and ready to accept stc transactions.
19 figure 22. write waveform ?set control register 1 to mir mode. figure 23. read waveform ?read from control register 2 (transmitter power level). (a) set control register 1 to mir mode address index c bit start start data sclk swdat srdat don't care led_dis 1st byte 2nd byte (internal) bus timing sample waveforms the following diagrams are sample waveforms for 2 byte write and read transactions and a 3 byte read transaction. start c bit index (b) read from control register 2 address start data sclk swdat srdat led_dis (internal) stc_rxd_en (internal) don't care 1st byte 2nd byte
20 the link distance testing was done using typical HSDL-3210 units with national semiconductor? pc87109 3v super i/o controller and smc? fdc37c669 and fdc37n769 super i/o controllers. an ir link distance of up to 40 cm was demonstrated for sir at full power. on the other ha nd, for mir at full power, an ir link distance of up to 35 cm was demonstrated. figure 24. extended index read waveform ?read device id. figure 25. timing diagram. (c) read device id start c bit index address start data sclk swdat srdat don't care led_dis (internal) start data don't care stc_rxd_en (internal) 1st byte 2nd byte 3rd byte sclk irtx/swdat irrx/srdat tckh tckl tckp tdotv tdoth tdls tdlh tdorv tdorh tdorf electrical specifications timing specifications are given in the table and diagram below. symbol parameter min. max. units tckp sclk clock period 250 ns tckh sclk clock high time 60 ns tckl sclk clock low time 80 ns tdotv output data valid (from infrared controller) 40 ns tdoth output data hold (from infrared controller) 0 ns tdorv output data valid (from optical transceiver) 40 ns tdorh output data hold (from optical transceiver) 40 ns tdorf line float delay 60 ns tdis input data setup 10 ns tdih input data hold 5 ns
21 appendix d: optical port dimensions for HSDL-3210 to ensure irda compliance, some constraints on the height and width of the window exist. the minimum dimensions ensure that the irda cone angles are met without vignetting. the maximum dimensions minimize the effects of stray light. the minimum size corresponds to a cone angle of 30? and the maximum size corre- sponds to a cone angle of 60?. in the figure below, x is the width of the window, y is the height of the window, and z is the distance from the HSDL-3210 to the back of the window. the distance from the center of the led lens to the center of the photodiode lens, k, is 5.1 mm. the equations for computing the window dimen- sions are as follows: x = k + 2*(z + d)*tana y = 2*(z + d)*tana the above equations assume that the thickness of the window is negligible compared to the dis- tance of the module from the back of the window (z). if they are comparable, z' replaces z in the above equation. z' is defined as: z' = z + t/n where ??is the thickness of the window and ??is the refractive index of the window material. the depth of the led image in- side the HSDL-3210, d, is 3.17 mm. ??is the required half angle for viewing. for irda com- pliance, the minimum is 15? and the maximum is 30?. assuming the thickness of the window to be negligible, the equations result in the following tables and graphs. d z k a ir transparent window opaque material opaque material ir transparent window x y figure 26. window design diagram.
module depth aperture width (x, mm) aperture height (y, mm) (z) mm max. min. max. min. 0 8.76 6.80 3.66 1.70 1 9.92 7.33 4.82 2.33 2 11.07 7.87 5.97 2.77 3 12.22 8.41 7.12 3.31 4 13.38 8.94 8.28 3.84 5 14.53 9.48 9.43 4.38 6 15.69 10.01 10.59 4.91 7 16.84 10.55 11.74 5.45 8 18.00 11.09 12.90 5.99 9 19.15 11.62 14.05 6.52 figure 28. aperture height (y) vs. module depth. figure 27. aperture width (x) vs. module depth. aperture width (x) mm 25 module depth (z) mm 10 47 0 09 15 26 20 5 135 8 aperture width (x) vs. module depth x max. x min. aperture height (y) mm 16 module depth (z) mm 8 47 0 09 10 26 4 135 8 aperture height (y) vs. module depth 14 12 6 2 y max. y min.
shape of the window from an optics standpoint, the window should be flat. this en- sures that the window will not alter either the radiation pattern of the led, or the receive pattern of the photodiode. if the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. while this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. the amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. the following drawings show the effects of a curved window on the radiation pattern. in all cases, the center thickness of the win- dow is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the trans- ceiver to the back surface of the window is 3 mm. window material almost any plastic material will work as a window material. poly- carbonate is recommended. the surface finish of the plastic should be smooth, without any texture. an ir filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. light loss should be measured at 875 nm. the recommended plastic materials for use as a cosmetic window are available from general electric plastics. recommended plastic materials: material light haze refractive number transmission index lexan 141l 88% 1% 1.586 lexan 920a 85% 1% 1.586 lexan 940a 85% 1% 1.586 note: 920a and 940a are more flame retardant than 141l. recommended dye: violet #21051 (ir transmissant above 625 nm). curved front and back (second choice) flat window (first choice) curved front, flat back (do not use) figure 29. shape of windows.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countrie s. data subject to change. copyright ?2006 avago technologies pte. all rights reserved. obsoletes 5988-8480en 5989-4390en may 28, 2006

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